The present invention relates to integrated circuit devices and, more particularly, to integrated circuit devices including a capacitor and methods of forming the same.
A capacitor formed in an integrated circuit device generally includes a dielectric layer sandwiched between two electrodes. Capacitors may be used in integrated circuit devices such as memory devices, analog devices including a RF device, mixed mode signal devices, system drivers and/or the like. Such capacitors typically require a specified capacitance to assure reliable operation in the respective applications. As the integration density of an integrated circuit device increases, however, the area occupied by a capacitor is typically reduced, which may reduce the capacitance of the capacitor. As such, various approaches have been proposed to form a capacitor with a high capacitance in a given area.
Typically, mono-crystalline silicon or polycrystalline silicon has been used as an electrode material for the capacitor. Mono-crystalline or polycrystalline silicon generally has an inherently limited ability to reduce a resistance of the electrode due to material characteristics of the silicon material. Additionally, a depletion region is typically generated in mono-crystalline or polycrystalline silicon electrode when a bias voltage is applied thereto, which may change the capacitance of a capacitor.
In an attempt to address these limitations associated with mono-crystalline or polycrystalline silicon electrode, it has been proposed to form a capacitor with a metal electrode. However, in forming a metal electrode, a temperature of about 600° C. may be required during processing, which may result in oxidization of other structures of the capacitor. As a result, a contact resistance may be raised and capacitance of the capacitor may be reduced.